1. Field of the Invention
The present invention relates to a semiconductor memory circuit, wherein it is attempted to prevent the degradation of read out performance because of the coupling capacity of the data line.
2. Description of the Related Art
In recent years, as the fining of the design rule of semiconductors advances, the fellow signal lines in a semiconductor chip have become easy to receive the interference by the coupling capacity.
Especially, a signal line with a fine potential change such as a data read out line of a memory cell, is easy to receive the influence of the coupling capacity generated between itself and a signal line having a large potential change and used in the peripheral circuits, and a malfunction such as a delay of read out or a reversing of the data in the worst case is caused by an influence thereof.
FIG. 1 is a circuit diagram showing an embodiment of the arrangement of a prior art semiconductor memory circuit (hereafter, referred to simply as a first prior art), and FIG. 2 is a figure of the operational wave form of the circuit shown in FIG. 1. In FIG. 1, numeral 401 is a memory cell, and numerals 402, 403 are complementary bit lines of the memory cell 401, and numerals 404, 405 and numerals 406, 407 are data read out lines, and numeral 408 is a precharge.multidot.balance line of the data read out lines, and numeral 409 is a word select line of the memory cell 401, and numeral 410 is a data select line. Furthermore, numeral 412 is a coupling capacity generated between the data read out line 406 and the data select line 410, and numeral 413 is a parasitic capacity held by the data read out line 406 itself, and numeral 414 is a parasitic capacity held by the data read out line 407 itself.
Next, the action of the above mentioned semiconductor memory circuit will be described by using FIG. 2. First, it is supposed that the bit lines 402, 403 and the data read out lines 404, 405, 406, 407 is initialized to be at "H" (high) level, by making the precharge.multidot.balance line 408 be at "L" (low) level. Furthermore, it is supposed that a sense amp active signal 421 which provides a constant current source and activates a sense amp 419 has also been activated sufficiently before the sense amp 419 operates.
If the data select line 410 is activated (becomes at "H" level) at the time t0, the potential of the data read out line 406 is raised by the coupling capacity 412, since the data select line 410 is a signal with a large potential change. If the word select line 409 is activated at the same time, the bit lines 402, 403 generate a level difference of "H" level and "L" level in accordance with the data held by the memory cell 401. Then, through PMOS transistors 415, 416 which have become in the on state by the activation of the data select line 410, the level of the bit lines 402, 403 is transmitted to the data read out lines 404, 405, and further, through bipolar transistors 417, 418, the data of the data read out lines 404, 405 is transmitted to the data read out lines 406, 407.
However, in the data read out line 406, the potential is raised to be higher than the potential in the initial state, when the data select line 410 is changed to be at "H" level because of the influence of the coupling capacity 412 between itself and the data select line 410. Therefore, even in the case where the data read out line 406 receives "L" data and the data read out line 407 receives "H" data, the potential of the read out line 406 is higher than the potential of the data read out line 407 just after the reception of the data, and the time .DELTA.t2 for the potential of the data read out line 406 to fall down to the potential at which the data of the data readout line 406 is recognized to be "L" data by the sense amp 419 at the next step, is long, and consequently, there has been such a problem that the time to perform a normal output is delayed.
Therefore, another embodiment of arrangement of a semiconductor memory circuit which has been thought out for improving the read out time, is shown in FIG. 3 (hereafter, referred to simply as a second prior art). FIG. 4 is a figure of the operational wave form of the circuit shown in FIG. 3. This second prior art is described in the patent publication (Japanese Patent Application Laid-Open No. 2-9086), and is an art wherein a shield line 622 as the earth potential is added for the measure of coupling.
Next, the action of the above mentioned semiconductor memory circuit will be described by using FIG. 4. Similarly to the previous prior art embodiment 1, if a data select line 610 and a word select line 609 are activated at the time t0, bit lines 602, 603 generate a level difference of "H" level and "L" level in accordance with the data held by a memory cell 601. Then, through PMOS transistors 615, 616 which have become in the on state by the activation of the data select line 610, the level of the bit lines 602, 603 is transmitted to data read out lines 604, 605, and further, the data of the data read out lines 604, 605 is transmitted to data read out lines 606, 607 through bipolar transistors 617, 618.
Here, the data read out line 606 is not affected by the coupling capacity of the data select line 610 because of a shield line 622, and even in the case where the data received by the data read out line 606 is "L" data, the time .DELTA.t3 for the potential of the data read out line 606 to fall down to the potential at which the data of the data read out line 606 is recognized to be "L" data by a sense amp 619 at the next step, is shorter than .DELTA.t2 in the first prior art. Consequently, the time to perform a normal output is improved.
However, in a case where the data read out line which is easy to receive an influence of the coupling and the data select line are formed in the same process and have a plane positional relation on the semiconductor process, it is necessary to arrange shield lines between all data read out lines and data select lines, and in the place where there are a lot of signal lines and which has a complex structure and is repeatedly arranged, such as a read out circuit section near the memory cell section, the occupied area on the semiconductor chip is increased, which is unsuitable for fining.
Furthermore, the characteristic deterioration arises in other circuits or signal lines, and the obstruction arises when the integration degree of a semiconductor chip is improved.
Moreover, in the case where the data read out line and the select signal line are formed in different processes and have a positional relation of a vertical structure in the multilayer interconnection process, it is required to vertically arrange the data read out line and the select signal line so as to be separated by a shield line of another process, in order to obtain the shield effect, and there has been such a problem that the manufacturing steps are increased and the structure becomes much more complex.